1. Field of the Invention
The present invention relates to a sample and hold circuit, and more particularly, to a sample and hold circuit employing a common negative input terminal and capable of avoiding the distortion of the sampling voltage resulted by the charge redistribution effect.
2. Description of the Related Art
FIG. 1A is a schematic drawing of a conventional sample and hold circuit. The sample apparatus receives an input voltage Vi, samples the received voltage and outputs the sampled voltage Vo. The sample and hold apparatus 100 includes switches 101˜104, capacitors 105 and 106 and an operation amplifier 108. The operation amplifier 108 includes an input stage 109 and an output stage 110, and a parasitic capacitor CP is present between the gate of the positive input terminal of the operation amplifier 108 and ground. FIG. 1B is a timing diagram of the control signals 10 and 20 in FIG. 1A. The control signal 10 controls the switches 102 and 103, while the control signal 20 controls the switches 101 and 104. A drawback of the conventional sample and hold circuit is that the sampled and held voltage contains an error produced by the effects of the charge redistribution of the capacitors, the clock feed-through, the channel charge injection and so on. In particular, the error voltage is varied with the different input voltage, which causes a nonlinear output with distortion. Referring to FIGS. 1A and 1B, for illustrating the effects, during the period between 0 and TA0, the control signal 10 takes a high level (assuming the switches are in high active operation). During the period, the switches 102 and 103 are short circuits, while the switches 101 and 104 are open circuits. Thus, the sampling voltage V1 of the capacitor 105 would be output to the amplifier 108 and the parasitic capacitor CP accordingly receives the sampling voltage V1 at this point. Meanwhile, the switch 103 is short circuited, thus, the capacitor 106 has a sampling voltage V2.
Afterwards, during the period between TB0 and TC0, the level of the control signal 10 is reduced, while the control signal 20 takes a high level. Thus, the switches 101 and 104 are short circuits and the switches 102 and 103 are open circuits. At this point, the voltage V2 of the capacitor 106 is output to the amplifier 108. Since the parasitic capacitor CP still retains a sampling voltage of V1 at this time, a charge redistribution effect occurs between the capacitor 106 and the parasitic capacitor CP. Assuming the capacitance of the capacitor 106 is M times that of the capacitance of the parasitic capacitor CP, the calculated voltage received by the operation amplifier 108 should be V2−[(V2−V1)/(1+M)], not the expected output value of V2, which causes a sampling voltage error. In order to reduce the sampling voltage error, the conventional sample and hold circuit reduces the error by increasing the capacitances of the capacitors 105 and 106. However, the increased capacitances not only increase the entire power consumption, but also slow down the sampling speed and require a larger chip area.
FIG. 2A is a schematic drawing of the operation amplifier of a conventional sample and hold circuit. The amplifier 208 herein has two positive terminals P10 and P20 and two negative terminals N10 and N20. The positive terminals P10 and P20 respectively receive two sampling voltages Vin1 and Vin2 which possess two different timings. The output voltage Vo is connected to both the negative terminals N10 and N20 for a feedback function. FIG. 2B is a schematic internal circuit drawing of the operation amplifier of a conventional sample and hold circuit in FIG. 2A. Referring to FIGS. 2A and 2B, the gates of transistors 21 and 24 serve as positive input terminals to receive the voltage Vin1 and Vin2, respectively. The gates of transistors 22 and 23 serve as negative input terminals to receive the voltage Vo for negative feedback. Thereafter, the transistors 21, 22, 23 and 24 are coupled to the output stage 210 to output the voltage Vo. The operation circuit of the conventional sample and hold circuit herein are designed using the transistors 22 and 23 to process the negative terminal inputs in the same functions but the different timings. Such a design scheme requires an increased area for the elements and chip. For the application of driving a display panel, the above-described design scheme would significantly increase the chip area since a display panel employs numerous sample and hold units.